1. Technical Field of the Invention
The present invention relates to the field of integrated circuit, and more particularly to three-dimensional memory (3D-M).
2. Prior Art
Three-dimensional memory (3D-M) is a monolithic semiconductor memory comprising a plurality of vertically stacked memory levels. It includes three-dimensional read-only memory (3D-ROM) and three-dimensional random-access memory (3D-RAM). The 3D-ROM can be further categorized into three-dimensional mask-programmed read-only memory (3D-MPROM) and three-dimensional electrically-programmable read-only memory (3D-EPROM). The 3D-EPROM could be one-time-programmable (3D-OTP) or multiple-time-programmable (3D-MTP). A 3D-M may further comprise at least one of a memristor, a resistive random-access memory (RRAM or ReRAM), a phase-change memory, a programmable metallization cell (PMC), a conductive-bridging random-access memory (CBRAM) or other memory devices.
U.S. Pat. No. 5,835,396 issued to Zhang on Nov. 3, 1998 discloses a 3D-ROM (FIG. 1A). It comprises a substrate 0 and a substrate circuit OK located thereon. An insulating dielectric 0d covers the substrate circuit OK and is planarized. A first memory level 10 is stacked above the insulating dielectric 0d, with a second memory level 20 stacked above the first memory level 10. The first and second memory levels 10, 20 are coupled to the substrate circuit OK through contact vias 13a, 23a, respectively.
Each of the memory levels (e.g. 10, 20) comprises a plurality of upper address-lines (i.e. y-lines, e.g. 12a-12d, 22a-22d), a plurality of lower address-lines (i.e. x-lines, e.g. 11a, 21a) and a plurality of memory devices (e.g. 1aa-1ad, 2aa-2ad) at the intersections between the upper and lower address-lines. Each memory level (e.g. 20) comprises at least a memory array (e.g. 200A). A memory array 200A is a collection of memory devices (e.g. 2aa-2ad) in a memory level 20 that share at least one address-line (e.g. 21a, 22a-22d). Within a single memory array 200A, all address-lines (e.g. 21a, 22a-22d) are continuous; between adjacent memory arrays, address-lines are not continuous.
A 3D-M die 1000 comprises a plurality of memory blocks (e.g. 1aa, 1ab . . . 1dd) (FIG. 1B). The structure shown in FIG. 1A is a portion of the memory block 1aa. In a memory block 1aa, its topmost memory level 20 comprises only a single memory array 200A. In other words, within the topmost memory level 20 of the memory block 1aa, all address-lines 21a, 22a-22d are continuous and terminate at or near the edge of the memory block 1aa. In prior art, all memory blocks (e.g. 1aa-1dd) in a 3D-M die 1000 have the same size; and, within each memory block 100, the memory arrays (e.g. 100A, 200A) in all memory levels (e.g. 10, 20) have the same size.
Each memory device 1aa is a two-terminal device having at least two possible states. Each memory device 1aa further comprises a diode or a diode-like device. To be more specific, the memory cell 1aa comprises a diode layer and a programmable layer. The diode layer is broadly interpreted as any layer whose resistance at the read voltage is substantially lower than when the applied voltage has a magnitude smaller than or polarity opposite to that of the read voltage. The states of the programmable layer (which represent the data stored therein) are written during manufacturing (i.e. mask-programmed, as in FIG. 1A) or after manufacturing (i.e. electrically-programmable).
When the storage capacity of a memory die is small, generally only a single type of information is stored in a single memory die. However, as the storage capacity of a 3D-M increases (e.g. a single 3D-M die can store 1 Tb and even higher), more types of information will be stored in a single 3D-M die. For example, both data (e.g. digital books, digital maps, digital music, digital movies, and/or digital videos) and codes (e.g. operating systems, software, and/or digital games) will be stored in a single 3D-M die. Although data may tolerate slow access, codes require fast access. Additionally, data generally has a stringent requirement on the memory cost. In prior art, all memory arrays (or, all memory blocks) in a 3D-M die have the same size. This causes several problems. If the memory array is too small, a high die cost may meet the cost requirement of the data. On the other hand, if the memory array is too large, slow access speed may not meet the speed requirement of the codes.